1. Field
Various features relate to Data Pattern Generation for Input/Output (I/O) Testing, and in particular to Pattern Generation for (I/O) Testing for a memory device in which the memory is fully usable during the I/O testing of multilevel interfaces.
2. Background
As data-rates continue to rise, off-chip input/output (I/O) characterization becomes increasingly critical. In the field, and even in test environments, I/O characterization is facilitated through built-in self-test (BIST) methods and hardware.
A BIST may serve to test the functionality of a device, characterized the device, and/or ascertain whether problems exist in the device. Sometimes, a BIST may incorrectly indicate a functional failure. For instance, there could be errors in a memory mechanism of a device itself that shows up as errors in the output, corrupting any analysis of the output performance. Traditionally, during some BIST tests, a write operation to the memory may be performed and then the memory is read out and tested to make sure the read/write operations worked correctly. The read and write functions may be correct, but a particular memory cell (e.g., a memory cell under test/use), is bad. Some internal structure along the data path to the memory cell may be bad. For example, a particular BIST test may measure data speed and accuracy across a data line and the BIST test may indicate a failure of the data line when actually the failure may be due to a faulty memory cell.
Typical BISTs employ binary data lines that allow for only binary signals. This hinders testing of devices that employ multi-level signaling which may allow for signals having three states or more.
Therefore, a method and/or device are needed that facilitate multi-level data pattern generation to enable to run a built-in self-test for a device without necessarily activating all the internal workings of the device.